1. Field of the Invention
The invention relates to device processing of silicon-on-insulator (SOI) wafers, and in particular to methods of forming SOI device with a front side contact to the underlying substrate of a SOI wafer.
2. Description of the Related Art
SOI technology has been shown to have many advantages over bulk silicon technology. These advantages include higher speed, low power and resistance to certain forms of radiation.
In many applications it is desirable to ground or bias the bottom substrate of a SOI circuit to prevent static charge build-up therein during normal chip operation. Static charge build-up may cause a back channel disturbing normal operation of SOI devices and creation of an electrical contact at the backside of the wafer requires additional wafer processing. In many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, creating a contact to substrate silicon via the back of the die is prohibitive. Therefore, the present inventors have determined that there is a need for a method of forming SOI device incorporating with at least one substrate contact contacting the substrate from the front side of a SOI wafer to allow biasing of the substrate through the electrically isolated buried oxide layer.
Ajmera et al., in U.S. Pat. No. 6,521,947, the entirety of which is hereby incorporated by reference, describe a method which includes the step of forming a contact trench in the substrate through the filled shallow isolation trench and silicon on insulator substrate region extending down at least to the top of a silicon substrate underlying the silicon on insulator region.
Fechner et al., in U.S. Pat. No. 6,300,666, the entirety of which is hereby incorporated by reference, describe a method which includes the step of forming a front side substrate contact on a silicon-on-insulator wafer in the presence of planarized contact dielectric for reducing the etching selectivity requirement, while allowing simultaneous etching and metallization of gate, source, drain and substrate contacts.
Brady et al., in U.S. Pat. No. 5,314,841, the entirety of which is hereby incorporated by reference, describe a method that includes contacting a front side to a SOI wafer. However, a trench is etched through the SOI layers to the substrate before any device-processing step. This trench is maintained during device processing and opened during source/drain implantation. An ohmic contact is made to the substrate when metallization thereof.